A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100×750 um^2. It consumes a total of 128 mW from a 1.2 V supply and a 2.5 V supply.
Publication: (1) W-H Tseng, C-W Fan, and J-T Wu, “A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz,” 2011 IEEE International Solid-State Circuits Conference, pp. 192-193, Feb. 2011. (2) W-H Tseng, C-W Fan, and J-T Wu, “A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With >70 dB SFDR up to 500 MHz,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 12, pp. 2845-2856, Dec. 2011.