An 8-bit subranging ADC was fabricated using a 55nm CMOS technology. To enhance speed, subranging is executed by activating comparators in the digital domain. To save power, comparators are latches with automatic offset calibration. Operating at 1GHz sampling rate, the ADC consumes 16mW from a 1.2V supply. The measured DNL is 0.8LSB and INL is 1.2LSB. The measured SFDR and SNDR are 55dB and 43.5dB respectively. The ADC occupies an active area of 0.2mm^2. Its FOM is 125fJ/conversion-step.
Publication: Y-H Chung and J-T Wu, “A 16-mW 8-Bit 1-GS/s Subranging ADC in 55nm CMOS,” 2011 Symposium on VLSI Circuits, pp. 128-129, June 2011.