A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. It combines low-complexity circuits and digital calibrations to achieve high speed and high performance. The DSM is a cascade of two second-order loops. It has a sampling rate of 1.1 GHz and an input bandwidth of 16.67 MHz with an oversampling ratio of 33. It uses high-speed opamps with a dc gain of only 10. Two different types of digital calibrations are used. We first employ the integrator leakage calibration to correct the poles of the integrators. We then apply the noise leakage calibration to minimize the leaking quantization noise from the first loop. The noise leakage calibration also relaxes the component-matching requirements. Both calibrations can operate in the background without interrupting the normal DSM operation. The chip’s measured signal-to-noise-and-distortion ratio and dynamic range are 74.32 and 81 dB, respectively. The chip consumes 94 mW from a 1 –V supply. The active area is 0.33 0.58 mm^2.
Publication: (1) S-H Wu and J-T Wu, “A 81-dB Dynamic Range 16-MHz Bandwidth DS Modulator Using Background Calibration,” IEEE Journal of Solid-State Circuits, Vol. 48, No. 9, pp. 2170-2179, Sept. 2013. (2) S-H Wu and J-T Wu, “Background Calibration of Integrator Leakage in Discrete-Time Delta-Sigma Modulators,” The 11th IEEE New Circuits and Systems Conference, pp. 1-4, June 2013.