A 10b 200MS/s dual-path pipelined ADC is fabricated in standard 65 nm CMOS technology. To reduce the power consumption, we propose a dual-path MDAC structure. We split the signal path into two paths, a coarse stage (CS) and a fine stage (FS). The residue amplification of the MDAC is performed first by the CS, and then by the FS. The requirements for the CS and FS are different. They can be designed and optimized seperately for the low power requirement. A dual-path opamp structure is utilied to implement the opamp used in coarse stage for performance improvement. We also employ the switching opamp technique to save more power. This ADC achieves 55dB SNDR over the whole nyquist band at 200 MS/s sampling rate while consuming 5.37 mW from a 1 V supply. The chip active area is 0.19 mm^2. The FOM is 48 fJ/conv.-step.
Publication: (1) Y Chai and J-T Wu, “A 5.37mW 10b 200MS/s Dual-Path Pipelined ADC,” 2012 IEEE International Solid-State Circuits Conference, pp. 462-463, Feb. 2012. (2) Y Chai and J-T Wu, “A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC,” IEEE Journal of Solid-State Circuits, Vol. 47, No. 12,, pp. 2905-2915, Dec. 2012.