An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.
Publications: (1) C-C Huang and J-T Wu, “A Background Comparator Calibration Technique for Flash Analog-to-Digital Converters,” IEEE Transactions on Circuits and Systems – I: Regular Papers, Vol. 52, No. 9, pp. 1732-1740, Sept. 2005. (2) C-Y Wang and J-T Wu, “A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection,” IEEE Transactions on Circuits and Systems – I: Regular Papers, Vol. 56, No. 6, pp. 1102-1114, June 2009. (3) C-C Huang, C-Y Wang, and J-T Wu, “A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration,” 2010 Symposium on VLSI Circuits, pp. 159-160, June 2010. (4) C-C Huang, C-Y Wang, and J-T Wu, “A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques,” IEEE Journal of Solid-State Circuits, Vol. 46, No. 4, pp. 848-858, April 2011.