A digital random-return-to-zero (DRRZ) technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90 nm CMOS technology. The DAC achieves a spurious-free dynamic range (SFDR) better than 60 dB for a sinewave input up to 460 MHz, and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.
Publication: W-H Tseng, J-T Wu, and Y-C Chu, “A CMOS 8-Bit 1.6-GS/s DAC with Digital Random Return-to-Zero,” IEEE Transactions on Circuits and Systems II: Express Briefs, Vol.58, No.1, pp. 1-5, Jan. 2011.