The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this work. Owing to the multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon con-trolled rectifier (SCR) path featuring a very low holding voltage is found in the experiment silicon chip. Such a parasitic path is first reported in the literatures. It may influence the electrostatic discharge (ESD) robustness of CMOS IC products with the HV and LV circuits integrated together. Thus, the layout rules at HV and LV interface should be carefully defined to avoid the occurrence of unexpected parasitic path.