Integrated circuits (ICs) are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all N-type transistor design. In such cases, the ESD protection circuit should only use N-type transistors to reduce the number of process masks required. This work proposes both a basic and an improved design for an all-NMOS power-rail ESD clamp. The improved design utilizes a current mirror circuit and NMOS string to reduce chip area and leakage, respectively. These ESD protection circuits have been implemented and validated in a 0.18μm CMOS process. The proposed designs are cost-effective and offer higher ESD robustness for practical applications.
C.-Y. Hsieh and Chun-Yu Lin, “All-NMOS power-rail ESD clamp circuit with compact area and low leakage,” IEEE Trans. Electron Devices, vol. 71, no. 9, pp. 5205-5211, Sep. 2024. DOI: 10.1109/TED.2024.3434776