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The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly … 閱讀全文… 關於 On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology

A 16-channel 12V-tolerant stimulator has been designed and successfully verified in a 0.18-μm 1.8-V/3.3-V CMOS process. It can be fully integrated with the microcontroller or the biomedical signal processor into an SoC chip fabricated in a low-voltage CMOS technology. The experimental results have shown that the proposed new digitally dynamic power supply technique for … 閱讀全文… 關於 A Digitally Dynamic Power Supply Technique for 16-Channel 12V-Tolerant Stimulator Realized in a 0.18-μm 1.8-V/3.3-V Low-Voltage CMOS Process

This paper presents a 16-channel closed-loop neuromodulation SoC for human seizure control. The SoC includes a 16-ch signal acquisition unit, a bio-signal processor, a 16-ch adaptive stimulator, and wireless telemetry. The signal acquisition unit amplifies and digitizes the sensed electrocorticogram (ECoG) signals. The digitized data are then processed by bio-signal processor … 閱讀全文… 關於 A Fully Integrated Closed-Loop Neuromodulation SoC with Wireless Power and Bidirectional Data Telemetry for Real-Time Human Epileptic Seizure Control

20140924演講公告 An RF Receiver Architecture for Intra-Band Carrier Aggregation 時間：2014/09/24(Wed.) 10:00-11:30 [請於09:50前入座] 地點：交通大學 交映樓1樓演講廳 講員：Prof. Behzad Razavi, University of California, Los Angeles 報名：http://goo.gl/y6f20J … 閱讀全文… 關於 An RF Receiver Architecture for Intra-Band Carrier Aggregation