因中度颱風蘇拉襲台，8/2(四)新竹已停班停課，此演講活動取消，以此通知，謝謝。 演講時間改為： 第一場：101年8月6日（一）上午10:00-11:30 台大電機二館 124 會議室 第二場：101年8月6日（一）下午15:30-17:00 交通大學工程四館528會議室 … 閱讀全文… 關於 【演講訊息】Sub-millimeter Wave CMOS Integrated Circuits and Systems
【演講訊息】Sub-millimeter Wave CMOS Integrated Circuits and Systems (Aug/02, 2012)
講員：Prof. Kenneth K. O (UT Dallas) 時間：101年08月02日(四) 15：20～17：00 地點：國立交通大學工程四館 424 會議室 大綱：CMOS (Complementary Metal Oxide Silicon) integrated circuits (IC’s) technology is emerging as a means for realization of capable and affordable systems that operate at 200 GHz and higher. The potential applications include spectroscopy for detection of harmful and dangerous chemicals, active … 閱讀全文… 關於 【演講訊息】Sub-millimeter Wave CMOS Integrated Circuits and Systems (Aug/02, 2012)
2012 Biomedical Circuits and Systems Conference (BioCAS)
會議名稱: Biomedical Circuits and Systems Conference (BioCAS) 會議日期: 2012/11/28 - 2012/11/30 會議地點: Sheraton Hotel, Hsinchu, Taiwan Important dates 2012/06/30 Deadline for Submission of Papers 2012/06/30 Deadline for Submission of Special Session Proposals 2012/07/02 Notification of Special Session Acceptance 2012/07/21 Deadline for Submission of Full Four-page Special Sessions … 閱讀全文… 關於 2012 Biomedical Circuits and Systems Conference (BioCAS)
Characterization of SOA in time domain and the improvement techniques for using in high-voltage integrated circuits
Safe operating area (SOA) in power semiconductors is one of the most important factors affecting device reliability. The SOA region of power MOSFETs must be well characterized for using in circuit design to meet the specification of applications, particularly including the time domain of circuit operations. In this paper, the characterization of SOA in the time domain is … 閱讀全文… 關於 Characterization of SOA in time domain and the improvement techniques for using in high-voltage integrated circuits
Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications
To meet the desired electrostatic discharge (ESD) robustness, ESD diodes was added into the I/O cells of integrated circuits (ICs). However, the parasitic capacitance from the ESD diodes often caused degradation on circuit performance, especially in the high-speed I/O applications. In this work, two modified layout styles to effectively improve the figures of merits (FOMs) of … 閱讀全文… 關於 Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications