Electrostatic Discharge (ESD) and electromigration are critical issues that significantly impact the reliability of integrated circuits (ICs). While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with … 閱讀全文… 關於 Characterization of ESD-Induced Electromigration on CMOS Metallization in On-Chip ESD Protection Circuit
研究成果
A Digital Jitter Compensation Technique for Analog-to-Digital Converters
For an ADC that periodically converts a time-varying analog input, the jitter in the ADC’s sampling clock introduces sampling errors, degrading the ADC’s dynamic performance. This paper describes a jitter compensation technique to mitigate the effect of sampling clock jitters. Clock jitter is detected by using an extra ADC that samples a reference clock. Sampling errors are … 閱讀全文… 關於 A Digital Jitter Compensation Technique for Analog-to-Digital Converters
Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process
A regulated cross-couple charge pump with new charging current smoothing technique is proposed and verified in a 0.18-μm 1.8-V/3.3-V CMOS process. The transient behaviors of 3-stage cross-couple charge pump and the expressions for the charging current are described in detail. The experiment results show that the charging current ripples are reduced by a factor of three through … 閱讀全文… 關於 Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process
A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
A novel horizontal n-channel junction field effect transistor (n-JFET) device is proposed and verified in a 0.25-µm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to … 閱讀全文… 關於 A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
Investigation on Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology
The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this work. Owing to the multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. However, a parasitic silicon … 閱讀全文… 關於 Investigation on Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology