The increasing complexity and integration of high-speed and high-frequency electronic systems have heightened the need for robust on-chip electrostatic discharge (ESD) protection to meet stringent reliability requirements. However, integrating ESD protection into these systems is challenging, as conventional protection devices introduce parasitic capacitance that degrades signal integrity, disrupts impedance matching, and limits bandwidth. This paper provides a comprehensive overview of modern on-chip ESD protection techniques tailored for high-speed and high-frequency applications. The discussion covers a range of strategies, including diode-based devices, silicon-controlled-rectifier (SCR)-based structures, stacked configurations, and the use of passive elements such as resistors, inductors, and T-coil. These approaches aim to achieve reliable ESD protection while maintaining signal performance across wide frequency bands. Additionally, this review highlights recent advancements in low-capacitance ESD structures and integration techniques that leverage parasitic components of protection circuits to complement signal path design. As electronic systems evolve toward higher frequencies, faster speeds, and greater integration, the development of compact, high-efficiency ESD protection circuits will remain a key enabler for future high-performance designs.
Chun-Yu Lin, “Review of low-C ESD protection designs for high-speed and high-frequency applications,” IEEE Trans. Electron Devices, vol. 72, no. 12, pp. 6411-6422, Dec. 2025, doi: 10.1109/TED.2025.3625953