吳介琮

For an ADC that periodically converts a time-varying analog input, the jitter in the ADC’s sampling clock introduces sampling errors, degrading the ADC’s dynamic performance. This paper describes a jitter compensation technique to mitigate the effect of sampling clock jitters. Clock jitter is detected by using an extra ADC that samples a reference clock. Sampling errors are … 閱讀全文… 關於 A Digital Jitter Compensation Technique for Analog-to-Digital Converters

A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. It combines low-complexity circuits and digital calibrations to achieve high speed and high performance. The DSM is a cascade of two second-order loops. It has a sampling rate of 1.1 GHz and an input bandwidth of 16.67 MHz with an oversampling ratio of 33. It uses high-speed … 閱讀全文… 關於 A 81-dB Dynamic Range 16-MHz Bandwidth DS Modulator Using Background Calibration

A 10-bit pipelined ADC was fabricated using a 65 nm CMOS technology. To reduce power consumption, switching opamps are used. These switching opamps are designed to have a short turn-on time. Digital background calibration is employed to correct the A/D conversion error caused by the low dc gain of the opamps. The biasing voltages in each opamp are automatically generated using … 閱讀全文… 關於 A 10-Bit 300-MS/s Pipelined ADC with Digital Calibration and Digital Bias Generation

A 10b 200MS/s dual-path pipelined ADC is fabricated in standard 65 nm CMOS technology. To reduce the power consumption, we propose a dual-path MDAC structure. We split the signal path into two paths, a coarse stage (CS) and a fine stage (FS). The residue amplification of the MDAC is performed first by the CS, and then by the FS. The requirements for the CS and FS are different. … 閱讀全文… 關於 A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC

An 8-bit subranging ADC was fabricated using a 55nm CMOS technology. To enhance speed, subranging is executed by activating comparators in the digital domain. To save power, comparators are latches with automatic offset calibration. Operating at 1GHz sampling rate, the ADC consumes 16mW from a 1.2V supply. The measured DNL is 0.8LSB and INL is 1.2LSB. The measured SFDR and SNDR … 閱讀全文… 關於 A 16-mW 8-Bit 1-GS/s Subranging ADC in 55nm CMOS