A new 2 × VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 × VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. This new design has a low standby leakage current by reducing the voltage difference across the gate oxide of the … 閱讀全文… 關於 New design of 2 × VDD-tolerant power-rail ESD clamp circuit for mixed-voltage IO buffers in 65-nm CMOS technology
柯明道
New 4-bit transient-to-digital converter for system-level ESD protection in display panels
A new on-chip 4-bit transient-to-digital converter for system-level electrostatic discharge (ESD) protection design is proposed. The proposed converter is designed to detect ESD-induced transient disturbances and transfer different ESD voltages into digital codes under system-level ESD tests. The experimental results in a 0.13-μm CMOS integrated circuit with 1.8-V devices have … 閱讀全文… 關於 New 4-bit transient-to-digital converter for system-level ESD protection in display panels
Stimulus driver for epilepsy seizure suppression with adaptive loading impedance
A stimulus driver circuit for micro-stimulator used in implantable device was presented in this paper. For epileptic seizure control, the target of the driver was to output 30-μA stimulus currents when the electrode impedance varied within 20 and 200 kΩ. The driver, which consisted of output stage, control block, and adaptor, has been integrated in a single chip. The averaged … 閱讀全文… 關於 Stimulus driver for epilepsy seizure suppression with adaptive loading impedance
互補式金氧半積體電路之靜電放電防護
靜電放電(Electrostatic Discharge, ESD)是造成大多數的電子元件或電子系統受到過度電性應力(Electrical Overstress, EOS)破壞的主要因素。這種破壞會導致半導體元件以及電腦系統等,形成一種永久性的毀壞,因而影響 積體電路(Integrated Circuits, … 閱讀全文… 關於 互補式金氧半積體電路之靜電放電防護