Integrated circuits (ICs) are susceptible to breakage due to electrostatic discharge (ESD), making ESD protection circuits necessary for ICs. In some applications, internal circuits may adopt an all N-type transistor design. In such cases, the ESD protection circuit should only use N-type transistors to reduce the number of process masks required. This work proposes both a … 閱讀全文… 關於 All-NMOS Power-Rail ESD Clamp Circuit with Compact Area and Low Leakage
研究成果
Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit
Electrostatic Discharge (ESD) and electromigration are critical issues that significantly impact the reliability of integrated circuits (ICs). While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with … 閱讀全文… 關於 Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit
A Digital Jitter Compensation Technique for Analog-to-Digital Converters
For an ADC that periodically converts a time-varying analog input, the jitter in the ADC’s sampling clock introduces sampling errors, degrading the ADC’s dynamic performance. This paper describes a jitter compensation technique to mitigate the effect of sampling clock jitters. Clock jitter is detected by using an extra ADC that samples a reference clock. Sampling errors are … 閱讀全文… 關於 A Digital Jitter Compensation Technique for Analog-to-Digital Converters
Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process
A regulated cross-couple charge pump with new charging current smoothing technique is proposed and verified in a 0.18-μm 1.8-V/3.3-V CMOS process. The transient behaviors of 3-stage cross-couple charge pump and the expressions for the charging current are described in detail. The experiment results show that the charging current ripples are reduced by a factor of three through … 閱讀全文… 關於 Regulated Charge Pump with New Clocking Scheme for Smoothing the Charging Current in Low Voltage CMOS Process
A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
A novel horizontal n-channel junction field effect transistor (n-JFET) device is proposed and verified in a 0.25-µm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries to … 閱讀全文… 關於 A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage